μ½˜ν…μΈ λ‘œ 이동

PCIe μš©μ–΄μ§‘

핡심 μš©μ–΄ ISO 11179 ν˜•μ‹ μ •μ˜.

A β€” ACK / ACS / AER / ATS

ACK (Acknowledge DLLP)

Definition. Receiver 의 Data Link Layer κ°€ LCRC 검증을 ν†΅κ³Όν•œ sequence number λ₯Ό λˆ„μ ν•˜μ—¬ sender μ—κ²Œ μ•Œλ¦¬λŠ” 8-byte DLLP.

Source. PCIe Base Spec, Data Link Layer.

Related. NAK, Sequence Number, Replay Buffer.

See also. Module 04

ACS (Access Control Services)

Definition. Switch 와 Root Port κ°€ P2P TLP λ₯Ό redirect / block 할지 κ²°μ •ν•˜λŠ” Capability 의 μ •μ±… λΉ„νŠΈ 집합.

Source. PCIe Base Spec, Extended Cap.

Related. P2P, IOMMU.

See also. Module 08

AER (Advanced Error Reporting)

Definition. PCIe 의 ν‘œμ€€ error reporting Extended Capability 둜, error λ₯Ό Correctable / Uncorrectable Non-Fatal / Uncorrectable Fatal 둜 λΆ„λ₯˜ν•΄ Status / Mask / Severity register 에 κΈ°λ‘ν•œλ‹€.

Source. PCIe Base Spec, Extended Cap ID 0x0001.

Related. ERR_COR, ERR_NONFATAL, ERR_FATAL Message.

See also. Module 07

ATS (Address Translation Service)

Definition. Device κ°€ IOMMU 에 IOVAβ†’PA λ³€ν™˜μ„ 미리 μš”μ²­ν•˜κ³  κ²°κ³Όλ₯Ό 자체 ATC (Address Translation Cache) 에 보관해 맀번 IOMMU walk λ₯Ό νšŒν”Όν•˜λŠ” λ©”μ»€λ‹ˆμ¦˜.

Source. PCIe Base Spec, Extended Cap ID 0x000F.

Related. PASID, PRI, IOMMU, ATC.

See also. Module 08

ASPM (Active State Power Management)

Definition. OS κ°œμž… 없이 link μžμ²΄κ°€ idle κ²€μΆœ ν›„ L0s / L1 둜 μžλ™ μ§„μž…ν•˜λŠ” power management λ©”μ»€λ‹ˆμ¦˜.

Source. PCIe Base Spec.

Related. L0s, L1, L1.1, L1.2.

See also. Module 07

B β€” BAR / BDF

BAR (Base Address Register)

Definition. Configuration Header 의 register (BAR0..BAR5) 둜, device 의 MMIO / IO μ˜μ—­μ˜ base μ£Όμ†Œμ™€ size λ₯Ό SW 에 μ•Œλ¦¬κ³  enumeration μ‹œ SW κ°€ base λ₯Ό ν• λ‹Ήν•œλ‹€.

Source. PCIe Base Spec, Type 0/1 Configuration Header.

Related. BAR sizing, Type bit, Prefetchable.

See also. Module 06

BDF (Bus / Device / Function)

Definition. PCIe 트리 μ•ˆμ—μ„œ ν•œ function 을 μ‹λ³„ν•˜λŠ” 16-bit μ‹λ³„μž (Bus 8-bit + Device 5-bit + Function 3-bit; ARI μ‚¬μš© μ‹œ Device 0 + Function 8-bit).

Source. PCIe Base Spec.

Related. Requester ID, ARI, Routing.

See also. Module 03, Module 06

C β€” CRS / CXL

CRS (Configuration Request Retry Status)

Definition. Device κ°€ link up 직후 enumeration μš”μ²­μ„ λ°›μ•˜μ„ λ•Œ 아직 ready κ°€ μ•„λ‹ˆλ©΄ 응닡 status 둜 λ³΄λ‚΄λŠ” μ½”λ“œ (0x2). SW λŠ” 일정 μ‹œκ°„ wait ν›„ μž¬μ‹œλ„ν•΄μ•Ό ν•œλ‹€.

Source. PCIe Base Spec, Completion Status.

Related. Boot hang, Vendor ID = 0xFFFF.

See also. Module 06

Definition. PCIe 의 PHY μœ„μ— 별도 Link Layer + 3 transport (CXL.io / .cache / .mem) λ₯Ό μ •μ˜ν•΄ cache-coherent accelerator 와 memory expansion 을 κ°€λŠ₯ν•˜κ²Œ ν•˜λŠ” alternate protocol.

Source. CXL Consortium Specifications 1.1 / 2.0 / 3.0 / 3.1.

Related. Type 1/2/3, Alternate Protocol Negotiation.

See also. Module 08

Configuration Space

Definition. 각 PCIe function 이 κ°€μ§€λŠ” 4 KB 의 register μ˜μ—­μœΌλ‘œ, 첫 64 byte 의 ν‘œμ€€ header (Type 0 λ˜λŠ” Type 1), 이후 PCI Capability list 와 Extended Capability list 둜 κ΅¬μ„±λœλ‹€.

Source. PCIe Base Spec.

Related. ECAM, Type 0, Type 1, Capability list.

See also. Module 06

D β€” DLLP

Definition. Data Link Layer 의 link-only 8-byte packet 으둜, Ack / Nak / FC Init/Update / PM / Vendor λ“±μ˜ type 을 가진닀.

Source. PCIe Base Spec, Data Link Layer.

Related. ACK, NAK, FC Update, TLP.

See also. Module 04

D-state

Definition. Device 의 power state (D0 active / D1 / D2 / D3hot / D3cold) 둜, OS / driver κ°€ PCI-PM Capability λ₯Ό 톡해 κ΄€λ¦¬ν•œλ‹€.

Source. PCIe Base Spec, PM Capability.

Related. L-state, PME.

See also. Module 07

E β€” ECAM / ECRC / EP / Equalization

ECAM (Enhanced Configuration Access Mechanism)

Definition. Configuration Space 4 KB 전체λ₯Ό MMIO μ˜μ—­μœΌλ‘œ mapping ν•΄ host SW κ°€ 일반 load/store 둜 access ν•˜λ„λ‘ ν•˜λŠ” λ©”μ»€λ‹ˆμ¦˜.

Source. PCIe Base Spec.

Related. Configuration Space, BDF.

See also. Module 06

ECRC (End-to-End CRC)

Definition. Transaction Layer 의 optional 32-bit CRC 둜, TLP header (λ³€κ²½ κ°€λŠ₯ field μ œμ™Έ) 와 payload μœ„λ‘œ κ³„μ‚°λ˜μ–΄ λΌμš°νŒ… λ…Έλ“œλ₯Ό 톡과해도 λ³€κ²½λ˜μ§€ μ•ŠλŠ”λ‹€.

Source. PCIe Base Spec, Transaction Layer.

Related. LCRC, AER.

See also. Module 03

Endpoint (EP)

Definition. PCIe 트리의 leaf device 둜 Type 0 Configuration Header λ₯Ό 가지며 NVMe / NIC / GPU λ“± μ‹€μ œ κΈ°λŠ₯을 μ œκ³΅ν•œλ‹€.

Source. PCIe Base Spec.

Related. Type 0, Switch, Root Complex.

See also. Module 01

Equalization

Definition. Gen3+ 의 Recovery μ•ˆμ˜ 4-phase 절차둜, μ–‘ 끝의 Tx FFE coefficient λ₯Ό receiver κ°€ ν˜‘μƒν•˜μ—¬ channel BER λ₯Ό μ΅œμ ν™”ν•œλ‹€.

Source. PCIe Base Spec, PHY Layer.

Related. Phase 0/1/2/3, Tx FFE, Rx CTLE/DFE, Preset.

See also. Module 05

F β€” FC / FLIT / FLR

FC (Flow Control)

Definition. Receiver 의 RX buffer 점유λ₯Ό sender 에 advertise ν•˜μ—¬ 솑신 속도λ₯Ό μ‘°μ ˆν•˜λŠ” credit-based λ©”μ»€λ‹ˆμ¦˜μœΌλ‘œ, Posted / Non-Posted / Completion 의 6 κ·Έλ£Ή (Header + Data) 으둜 κ΅¬μ„±λœλ‹€.

Source. PCIe Base Spec, Transaction Layer + Data Link Layer.

Related. InitFC1/InitFC2, UpdateFC, VC.

See also. Module 04

FLIT (Flow Control unIT)

Definition. Gen6+ 의 κ³ μ • 256-byte ν”„λ ˆμž„ λ‹¨μœ„λ‘œ, TLP/DLLP λ₯Ό ν•¨κ»˜ λ‹΄μ•„ framing λ‹¨μˆœν™” + FEC 톡합 + ACK/NAK λ©”μ»€λ‹ˆμ¦˜ λ‹¨μˆœν™”λ₯Ό λ‹¬μ„±ν•œλ‹€.

Source. PCIe Base Spec 6.0.

Related. PAM4, FEC.

See also. Module 04, Module 05

FLR (Function-Level Reset)

Definition. Device Control register 의 Initiate FLR bit 으둜 νŠΈλ¦¬κ±°λ˜μ–΄ ν•œ function 만 logical reset ν•˜λŠ” λ©”μ»€λ‹ˆμ¦˜μœΌλ‘œ, in-flight TLP drop + 일뢀 register reset ν›„ 100 ms μ•ˆμ— λ‹€μ‹œ μ‚¬μš© κ°€λŠ₯해진닀.

Source. PCIe Base Spec.

Related. Hot Reset, Secondary Bus Reset.

See also. Module 06

L β€” L-state / LCRC / LTSSM

L-state

Definition. Link 의 LTSSM μƒνƒœ (L0 / L0s / L1 / L1.1 / L1.2 / L2) 둜, 각자 λ‹€λ₯Έ μ ˆμ „ μˆ˜μ€€κ³Ό exit latency λ₯Ό 가진닀.

Source. PCIe Base Spec, Physical Layer.

Related. ASPM, D-state.

See also. Module 05, Module 07

Definition. Data Link Layer κ°€ TLP + Sequence # μœ„λ‘œ κ³„μ‚°ν•˜λŠ” 32-bit CRC 둜, hop-level (link 단일 segment) 무결성을 보μž₯ν•œλ‹€.

Source. PCIe Base Spec, Data Link Layer.

Related. ECRC, Replay Buffer.

See also. Module 02, Module 04

Definition. Physical Layer 의 11-state state machine 으둜 Detect β†’ Polling β†’ Configuration β†’ L0 β†’ L0s/L1/L2/Recovery/Disabled/Loopback/Hot Reset 의 link μƒνƒœ 전이λ₯Ό κ΄€λ¦¬ν•œλ‹€.

Source. PCIe Base Spec, Physical Layer.

Related. TS1/TS2, Equalization.

See also. Module 05

M β€” MPS / MRRS / MSI / MSI-X

MPS (Max Payload Size)

Definition. Device κ°€ ν•œ TLP 둜 보낼 수 μžˆλŠ” μ΅œλŒ€ data payload size 둜, 128 / 256 / 512 / 1024 / 2048 / 4096 byte 쀑 link μ–‘ 끝의 capability 의 minimum 이 μ‚¬μš©λœλ‹€.

Source. PCIe Base Spec, PCIe Capability.

Related. MRRS, TLP Length.

See also. Module 03

MRRS (Max Read Request Size)

Definition. Requester κ°€ ν•œ 번의 Memory Read Request 둜 μš”μ²­ν•  수 μžˆλŠ” μ΅œλŒ€ byte 둜, MPS 와 λ³„λ„λ‘œ μ„€μ •λœλ‹€.

Source. PCIe Base Spec, PCIe Capability.

Related. MPS, Tag.

See also. Module 03

MSI / MSI-X

Definition. Memory Write TLP ν˜•μ‹μ˜ in-band interrupt λ©”μ»€λ‹ˆμ¦˜μœΌλ‘œ, MSI λŠ” 1-32 vector, MSI-X λŠ” μ΅œλŒ€ 2048 vector 와 vector 별 mask λ₯Ό μ§€μ›ν•œλ‹€.

Source. PCIe Base Spec, PCI Capability ID 0x05 / 0x11.

Related. Legacy INTx.

See also. Module 06

N β€” NAK / NP

NAK (Negative Acknowledge DLLP)

Definition. Receiver 의 LCRC 검증 μ‹€νŒ¨ λ˜λŠ” sequence number μœ„λ°˜ μ‹œ sender μ—κ²Œ μž¬μ†‘μ‹ μ„ μš”μ²­ν•˜λŠ” 8-byte DLLP.

Source. PCIe Base Spec, Data Link Layer.

Related. Replay Buffer, Sequence Number.

See also. Module 04

Non-Posted (NP)

Definition. Completion (Cpl λ˜λŠ” CplD) 응닡이 ν•„μˆ˜μΈ TLP μΉ΄ν…Œκ³ λ¦¬λ‘œ, MRd, IORd, IOWr, CfgRd/Wr, AtomicOp κ°€ ν•΄λ‹Ήλœλ‹€.

Source. PCIe Base Spec.

Related. Posted, Completion, Credit groups.

See also. Module 03

P β€” PASID / P2P / PHY / Posted / PRI

PASID (Process Address Space ID)

Definition. TLP 의 PASID prefix/extension 으둜 μš΄λ°˜λ˜λŠ” 20-bit μ‹λ³„μžλ‘œ, IOMMU κ°€ device 의 DMA λ₯Ό μ–΄λŠ process 의 address space 둜 맀핑할지 κ²°μ •ν•˜κ²Œ ν•œλ‹€.

Source. PCIe Base Spec, Extended Cap ID 0x0023.

Related. ATS, IOMMU, SVM.

See also. Module 08

P2P (Peer-to-Peer DMA)

Definition. 두 Endpoint κ°€ Root Complex λ₯Ό κ±°μΉ˜μ§€ μ•Šκ³  Switch μ•ˆμ—μ„œ 직접 DMA ν•˜λŠ” traffic pattern.

Source. PCIe Base Spec.

Related. ACS, GPU↔NIC, NCCL.

See also. Module 08

Physical Layer (PHY)

Definition. PCIe 의 μ΅œν•˜μœ„ κ³„μΈ΅μœΌλ‘œ Framing / Encoding / Scrambling / SerDes / LTSSM / Equalization 을 λ‹΄λ‹Ήν•œλ‹€.

Source. PCIe Base Spec, Physical Layer.

Related. PCS, PMA, Lane.

See also. Module 02, Module 05

Posted (P)

Definition. TL-level 응닡이 μ—†λŠ” TLP μΉ΄ν…Œκ³ λ¦¬ (MWr, MsgD) 둜, DLL 의 ACK/NAK 은 λ°›μ§€λ§Œ application-level completion 은 별도이닀.

Source. PCIe Base Spec.

Related. Non-Posted, Completion.

See also. Module 03

PRI (Page Request Interface)

Definition. Device κ°€ ATS 의 page fault λ₯Ό OS / IOMMU 에 μ•Œλ € page-in ν›„ μž¬μ‹œλ„ν•˜λ„λ‘ ν•˜λŠ” λ©”μ»€λ‹ˆμ¦˜.

Source. PCIe Base Spec, Extended Cap ID 0x0013.

Related. ATS, ODP.

See also. Module 08

R β€” RC / Replay Buffer / Routing

Root Complex (RC)

Definition. CPU ↔ PCIe λ„λ©”μΈμ˜ κ²Œμ΄νŠΈμ›¨μ΄λ‘œ, Root Port κ°€ λ‹€μš΄μŠ€νŠΈλ¦Ό link 의 μ‹œμž‘μ μ΄λ©° memory controller 와 합쳐진 κ²½μš°κ°€ λ§Žλ‹€.

Source. PCIe Base Spec.

Related. Switch, Endpoint, Bridge.

See also. Module 01

Replay Buffer

Definition. Sender 의 Data Link Layer κ°€ ACK λ°›κΈ° μ „κΉŒμ§€ μ†‘μ‹ ν•œ TLP λ₯Ό λ³΄κ΄€ν•˜λŠ” buffer 둜, NAK μ‹œ κ·Έ sequence number λΆ€ν„° μž¬μ†‘μ‹ ν•œλ‹€.

Source. PCIe Base Spec, Data Link Layer.

Related. ACK, NAK, Sequence Number.

See also. Module 04

S β€” SerDes / Sequence Number / SR-IOV / Switch

SerDes (Serializer/Deserializer)

Definition. 병렬 데이터λ₯Ό 직렬 differential signal 둜 λ³€ν™˜ (Tx) ν•˜κ³  직렬 μ‹ ν˜Έλ₯Ό λ³‘λ ¬λ‘œ 볡원 (Rx) ν•˜λŠ” PHY 의 analog block.

Source. PCIe Base Spec, PHY.

Related. PMA, CDR.

See also. Module 05

Sequence Number

Definition. Data Link Layer κ°€ 솑신 TLP λ§ˆλ‹€ λΆ€μ—¬ν•˜λŠ” 12-bit (modulo 4096) 순차 번호둜, ACK / NAK / Replay Buffer 의 기쀀이 λœλ‹€.

Source. PCIe Base Spec, Data Link Layer.

Related. ACK, NAK, Replay Buffer.

See also. Module 04

SR-IOV (Single-Root I/O Virtualization)

Definition. ν•œ PCIe device κ°€ μ—¬λŸ¬ lightweight Virtual Function (VF) 을 expose ν•΄, 각 VF κ°€ 별도 BDF + 별도 BAR + 별도 MSI-X λ₯Ό 가지고 hypervisor κ°€ κ²ŒμŠ€νŠΈμ— 직접 νŒ¨μŠ€μŠ€λ£¨ν•  수 있게 ν•˜λŠ” λ©”μ»€λ‹ˆμ¦˜.

Source. PCIe Base Spec, Extended Cap ID 0x0010.

Related. PF, VF, ARI, IOMMU.

See also. Module 08

Switch

Definition. PCIe 의 fan-out λ””λ°”μ΄μŠ€λ‘œ upstream port 1 + downstream port N 을 가지고 TLP λ₯Ό λΌμš°νŒ…ν•œλ‹€.

Source. PCIe Base Spec.

Related. Type 1 Header, Bridge.

See also. Module 01

T β€” Tag / TC / TLP / Type 0 / Type 1

Tag

Definition. Non-Posted Request λ§ˆλ‹€ Requester κ°€ λΆ€μ—¬ν•˜λŠ” 8-bit (extended μ‹œ 10-bit) μ‹λ³„μžλ‘œ, Completion 맀칭에 μ‚¬μš©λœλ‹€.

Source. PCIe Base Spec, TLP Header.

Related. Outstanding NP, Cpl.

See also. Module 03

TC (Traffic Class)

Definition. TLP header 의 3-bit ν•„λ“œλ‘œ Virtual Channel (VC) 맀핑에 μ‚¬μš©λ˜λŠ” μš°μ„ μˆœμœ„ μ‹λ³„μž.

Source. PCIe Base Spec, TLP Header.

Related. VC, ATTR.

See also. Module 03

TLP (Transaction Layer Packet)

Definition. Transaction Layer 의 packet 으둜, header (3DW λ˜λŠ” 4DW) + payload (0..4096 byte) + optional ECRC 의 ꡬ쑰λ₯Ό 가진닀.

Source. PCIe Base Spec, Transaction Layer.

Related. Fmt, Type, DLLP.

See also. Module 03

Type 0 / Type 1 (Configuration Header)

Definition. Type 0 = Endpoint 의 64-byte Configuration Header (BAR0..5 λ“±), Type 1 = Bridge / Switch port 의 64-byte Configuration Header (Sec/Sub Bus #, Mem/IO Base/Limit λ“±).

Source. PCIe Base Spec.

Related. BDF, BAR.

See also. Module 06

V β€” VC

VC (Virtual Channel)

Definition. 물리 link μœ„μ—μ„œ 독립적인 buffer + flow control credit 을 κ°€μ§€λŠ” 가상 μ±„λ„λ‘œ, 0..7 의 ID λ₯Ό 가진닀 (λŒ€λΆ€λΆ„ μ‹œμŠ€ν…œμ€ VC0 만 μ‚¬μš©).

Source. PCIe Base Spec, Extended Cap ID 0x0002.

Related. TC, FC.

See also. Module 04

μΆ”κ°€ ν•­λͺ© (Phase 2 κ²€μˆ˜ μ™„λ£Œ)

IOV (I/O Virtualization)

Definition. PCIe λ””λ°”μ΄μŠ€λ₯Ό λ‹€μˆ˜μ˜ 가상 머신에 λΆ„ν•  λ…ΈμΆœν•˜λŠ” 가상화 기술 ꡰ의 총칭으둜, SR-IOV / MR-IOV 등을 ν¬ν•¨ν•œλ‹€.

Source. PCIe SIG IOV ECN; PCIe Base Spec ATS/PRI Annex.

Related. SR-IOV, VF, PF, ATS.

See also. Module 03, Module 06

SR-IOV (Single-Root I/O Virtualization)

Definition. 단일 PCIe Root Complex ν•˜μ˜ λ””λ°”μ΄μŠ€κ°€ PF 1κ°œμ™€ λ‹€μˆ˜ VF λ₯Ό μ œκ³΅ν•΄ hypervisor 우회 (kernel bypass) 가상화λ₯Ό μ§€μ›ν•˜λŠ” ν‘œμ€€.

Source. PCI SIG, SR-IOV 1.1 Specification.

Related. PF, VF, IOV, BAR, ATS.

See also. Module 06

FEC (Forward Error Correction)

Definition. PCIe Gen6 μ΄μƒμ—μ„œ PAM4 μ‹ ν˜Έμ˜ BER λ₯Ό λ³΄μƒν•˜κΈ° μœ„ν•΄ 솑신츑이 redundancy μ½”λ“œλ₯Ό μΆ”κ°€ν•˜κ³  μˆ˜μ‹ μΈ‘μ΄ μ •μ •ν•˜λŠ” link-layer κΈ°λŠ₯.

Source. PCIe Base Spec 6.0, Β§4.5 (Flit Mode FEC).

Related. PAM4, Flit Mode, LCRC, ECRC.

See also. Module 05, Module 08

CDR (Clock-Data Recovery)

Definition. Receiver κ°€ incoming serial bitstream 의 transition μœΌλ‘œλΆ€ν„° sampling clock 을 λ³΅μ›ν•˜λŠ” PHY block.

Source. PCIe Base Spec β€” Physical Layer; common SerDes terminology.

Related. Equalization, Deskew, Symbol/Block Alignment.

See also. Module 05

ARI (Alternative Routing-ID Interpretation)

Definition. 단일 device function 수λ₯Ό 8 β†’ 256 으둜 ν™•μž₯ν•˜κΈ° μœ„ν•΄ BDF 의 Device ν•„λ“œλ₯Ό Function ν•„λ“œλ‘œ μž¬ν•΄μ„ν•˜λŠ” PCIe Capability.

Source. PCIe Base Spec β€” ARI Capability.

Related. BDF, SR-IOV, PF, VF.

See also. Module 06

PAM4 (4-level Pulse Amplitude Modulation)

Definition. ν•œ 심볼에 2λΉ„νŠΈλ₯Ό 맀핑(00/01/10/11)ν•˜μ—¬ 동일 baud rate μ—μ„œ λ°μ΄ν„°μœ¨μ„ 두 배둜 λŠ˜λ¦¬λŠ” PCIe Gen6 의 μ‹ ν˜Έ λ³€μ‘° 방식.

Source. PCIe Base Spec 6.0, Β§4.

Related. NRZ, FEC, Flit Mode, link training.

See also. Module 05, Module 08

Definition. PCIe Physical Layer κ°€ link 의 detect / polling / configuration / L0 / L1 / recovery λ“± μƒνƒœ 전이λ₯Ό κ΄€λ¦¬ν•˜λŠ” ν‘œμ€€ FSM.

Source. PCIe Base Spec β€” Physical Layer LTSSM.

Related. TS1, TS2, Recovery, Polling, Detect, L0, L0s.

See also. Module 05

IOMMU (I/O Memory Management Unit)

Definition. PCIe / AMBA λ””λ°”μ΄μŠ€μ˜ DMA μ£Όμ†Œλ₯Ό μ‹œμŠ€ν…œ λ©”λͺ¨λ¦¬μ˜ 가상 μ£Όμ†Œ β†’ 물리 μ£Όμ†Œλ‘œ λ³€ν™˜ν•˜κ³  보호 검사λ₯Ό μˆ˜ν–‰ν•˜λŠ” ν•˜λ“œμ›¨μ–΄ μœ λ‹›μœΌλ‘œ, κ°€μƒν™”Β·λ³΄μ•ˆ λͺ¨λ‘μ— μ‚¬μš©λœλ‹€.

Source. Intel VT-d, AMD-Vi, ARM SMMU spec.

Related. ATS, PRI, SR-IOV, MMU.

See also. Module 06

MMIO (Memory-Mapped I/O)

Definition. λ””λ°”μ΄μŠ€ λ ˆμ§€μŠ€ν„°λ₯Ό μ‹œμŠ€ν…œ λ©”λͺ¨λ¦¬ μ£Όμ†Œ 곡간에 λ§€ν•‘ν•˜μ—¬ 일반 load/store λͺ…λ ΉμœΌλ‘œ μ ‘κ·Όν•˜λ„λ‘ ν•˜λŠ” 방식.

Source. PCIe Base Spec β€” Configuration & BAR.

Related. BAR, Type 0/1 Header, prefetchable region.

See also. Module 06