μ½μ€ κ°μ
νμ΅ νλ¦
M01 PCIe λκΈ° β M02 3-Layer β M03 TLP
β
M04 DLLP & FC
β
M05 PHY & LTSSM
β
M06 Config & Enumeration
β
M07 Power / AER / HP
β
M08 SR-IOV / ATS / P2P / CXL
β
Quick Reference Card (M09)
λͺ¨λλ³ ν΅μ¬ μ°μΆλ¬Ό
| λͺ¨λ |
μ£Όμ μ°μΆλ¬Ό |
| M01 |
"μ PCIe?" μ€λͺ
, Gen1~Gen7 ν |
| M02 |
3-Layer μ±
μ λ€μ΄μ΄κ·Έλ¨ |
| M03 |
TLP header field ν, μ£Όμ type μΉ΄νλ‘κ·Έ |
| M04 |
ACK/NAK timeline, FC credit ν |
| M05 |
LTSSM μν μ μ΄λ, equalization phase |
| M06 |
Type 0/1 header λΉκ΅, BAR sizing μμ |
| M07 |
D/L state matrix, AER hierarchy |
| M08 |
SR-IOV PF/VF λͺ¨λΈ, CXL.io vs cache vs mem |
μκ° κ°μ΄λ
- λΉ λ₯΄κ² νκΈ°: M01-M03 (2-3μκ°) + M09 (30λΆ)
- DV μμ§λμ΄ κΆμ₯: μ λͺ¨λ (10-15μκ°)
- HW μ€κ³μ: M02-M07 (8-10μκ°)
- SW (driver/firmware): M01, M03, M06-M07 (5-7μκ°)