์ฝ˜ํ…์ธ ๋กœ ์ด๋™

SoC Secure Boot ์šฉ์–ด์ง‘

ํ•ต์‹ฌ ์šฉ์–ด ISO 11179 ํ˜•์‹ ์ •์˜.


A โ€” Anti-Rollback / Attestation

Anti-Rollback

Definition. Image์˜ ์ด์ „ ๋ฒ„์ „์œผ๋กœ downgrade๋ฅผ ์ฐจ๋‹จํ•˜๋Š” ๋ฉ”์ปค๋‹ˆ์ฆ˜์œผ๋กœ, OTP fuse counter๋ฅผ ํ†ตํ•ด minimum acceptable version์„ ๊ฐ•์ œ.

Source. Secure Boot literature.

Related. Version counter, OTP fuse, security patch.

Attestation

Definition. Device๊ฐ€ ์ž์‹ ์˜ boot state๋ฅผ ์™ธ๋ถ€์— ์ฆ๋ช…ํ•˜๋Š” ๋ฉ”์ปค๋‹ˆ์ฆ˜์œผ๋กœ, TPM PCR ๋˜๋Š” secure enclave๊ฐ€ ์„œ๋ช…ํ•œ measurement๋ฅผ ์‚ฌ์šฉ.

Source. TPM 2.0 spec.

Related. Measured Boot, PCR, remote attestation.


B โ€” BootROM / BL1-3

BootROM

Definition. SoC์— mask ROM์œผ๋กœ ๊ณ ์ •๋œ ์ฒซ ์‹คํ–‰ ์ฝ”๋“œ๋กœ, ๋ณ€๊ฒฝ ๋ถˆ๊ฐ€๋Šฅํ•œ trust anchor ์—ญํ• .

Source. SoC architecture.

Related. HW RoT, mask ROM, BL1.

BL1 / BL2 / BL31 / BL33

Definition. ARM Trusted Firmware์˜ boot loader ๋‹จ๊ณ„ โ€” BootROM โ†’ BL1 (trusted boot init) โ†’ BL2 (DRAM init + BL31/33 load) โ†’ BL31 (EL3 secure monitor) โ†’ BL33 (U-Boot/non-secure).

Source. ARM Trusted Firmware.

See also. Module 02


C โ€” Chain of Trust / Crypto Agility

Chain of Trust

Definition. ๊ฐ boot ๋‹จ๊ณ„๊ฐ€ ๋‹ค์Œ ๋‹จ๊ณ„์˜ ์„œ๋ช…์„ ๊ฒ€์ฆํ•œ ํ›„์—๋งŒ control์„ ๋„˜๊ธฐ๋Š” ์‹ ๋ขฐ ์ „ํŒŒ ํŒจํ„ด.

Source. Verified Boot architectures.

Related. Verify-then-execute, HW RoT.

See also. Module 02

Crypto Agility

Definition. ์•”ํ˜ธ ์•Œ๊ณ ๋ฆฌ์ฆ˜์„ ๋ณ€๊ฒฝ ๊ฐ€๋Šฅํ•˜๊ฒŒ ์„ค๊ณ„ํ•˜๋Š” ์›์น™์œผ๋กœ, RSA โ†’ PQC (Post-Quantum Cryptography) ๊ฐ™์€ ๋งˆ์ด๊ทธ๋ ˆ์ด์…˜ ๋Œ€๋น„.

Source. NIST PQC standardization.


E โ€” eFuse / ECDSA

eFuse

Definition. Electrically programmable fuse๋กœ, OTP ๋ฉ”๋ชจ๋ฆฌ์˜ ํ•œ ํ˜•ํƒœ. ํ•œ ๋ฒˆ blowํ•˜๋ฉด ์˜๊ตฌ์ ์œผ๋กœ 1.

Source. Silicon technology.

Related. OTP, immutable storage.

ECDSA

Definition. Elliptic Curve Digital Signature Algorithm. RSA๋ณด๋‹ค ์ž‘์€ key/signature ํฌ๊ธฐ๋กœ ๋™๋“ฑ ๋ณด์•ˆ ์ œ๊ณต.

Source. FIPS 186.

Common curves. P-256, P-384, secp256k1.


F โ€” Fault Injection

Fault Injection (FI)

Definition. ์ „์•• ๊ธ€๋ฆฌ์น˜, ํด๋Ÿญ ๊ธ€๋ฆฌ์น˜, ๋ ˆ์ด์ €, X-ray ๋“ฑ์œผ๋กœ ์˜๋„์  hardware fault๋ฅผ ์œ ๋ฐœํ•ด signature ๊ฒ€์ฆ์„ ์šฐํšŒํ•˜๋Š” ๊ณต๊ฒฉ ๊ธฐ๋ฒ•.

Source. Hardware security research.

Related. Glitch detector, FROST, Glitchy Descriptor attack.

See also. Module 05


H โ€” HSM / HW RoT

HSM (Hardware Security Module)

Definition. ์•”ํ˜ธ ํ‚ค ์ƒ์„ฑ/์ €์žฅ/์‚ฌ์šฉ์„ ์•ˆ์ „ํ•œ hardware ์•ˆ์—์„œ๋งŒ ์ˆ˜ํ–‰ํ•˜๋Š” ์™ธ๋ถ€ module๋กœ, Production private key ๊ด€๋ฆฌ์— ํ•„์ˆ˜.

Source. FIPS 140-⅔.

HW RoT (Hardware Root of Trust)

Definition. Boot ์‹ ๋ขฐ์˜ ์ถœ๋ฐœ์ ์œผ๋กœ mask ROM (BootROM) + OTP (ROTPK hash + ๋ณด์•ˆ ์„ค์ •)๋กœ ๊ตฌ์„ฑ.

Source. Secure Boot literature.

See also. Module 01


M โ€” Measured Boot

Measured Boot

Definition. ๊ฐ boot ๋‹จ๊ณ„์˜ image hash๋ฅผ TPM PCR (Platform Configuration Register)์— ๋ˆ„์ ํ•˜์—ฌ OS๊ฐ€ boot history๋ฅผ ๊ฒ€์ฆํ•  ์ˆ˜ ์žˆ๊ฒŒ ํ•˜๋Š” ๊ธฐ๋ฒ•.

Source. TPM 2.0 spec.

Related. PCR, attestation, Verified Boot ๋น„๊ต.

See also. Module 02


O โ€” OTP

OTP (One-Time Programmable)

Definition. 1ํšŒ๋งŒ ์“ฐ๊ธฐ ๊ฐ€๋Šฅํ•œ ๋น„ํœ˜๋ฐœ์„ฑ ๋ฉ”๋ชจ๋ฆฌ๋กœ, ROTPK hash + ๋ณด์•ˆ ์„ค์ • + lifecycle state ์ €์žฅ.

Source. Silicon technology.

Related. eFuse, mask ROM, ROTPK.

See also. Module 01


R โ€” ROTPK / RSA

ROTPK (Root of Trust Public Key)

Definition. Boot ๊ฒ€์ฆ์˜ ์ตœ์ƒ์œ„ public key๋กœ, hash๊ฐ€ OTP์— ์ €์žฅ๋˜์–ด BootROM์ด ๋น„๊ต ๊ฒ€์ฆ.

Source. Trusted Firmware spec.

See also. Module 01

RSA

Definition. Rivest-Shamir-Adleman ๋น„๋Œ€์นญ ์•”ํ˜ธ ์•Œ๊ณ ๋ฆฌ์ฆ˜. Boot signature์— RSA-2048/4096 ์‚ฌ์šฉ.

Source. PKCS #1, RFC 8017.

Related. PKCS#1 v1.5, PSS padding.


S โ€” SHA / Side-Channel

SHA-256 / SHA-384

Definition. Secure Hash Algorithm 2 family. Boot image hash + signature ๊ณ„์‚ฐ์— ์‚ฌ์šฉ.

Source. FIPS 180-4.

Side-Channel Attack

Definition. Power consumption, EM emission, timing ์ธก์ •์œผ๋กœ ํ‚ค๋‚˜ secret๋ฅผ ์ถ”์ถœํ•˜๋Š” ๊ณต๊ฒฉ.

Source. Cryptographic literature.

Related. Constant-time crypto, masking, blinding.

See also. Module 05


V โ€” Verified Boot

Verified Boot

Definition. Boot ์‹œ signature ๊ฒ€์ฆ์œผ๋กœ image์˜ ์ธ์ฆ์„ฑ์„ ํ™•์ธํ•˜๊ณ , ์‹คํŒจ ์‹œ boot๋ฅผ ์ฐจ๋‹จํ•˜๋Š” enforcement ๊ธฐ๋ฒ•.

Source. Verified Boot architectures.

Related. Measured Boot ๋น„๊ต, anti-rollback.

See also. Module 02


์ถ”๊ฐ€ ์•ฝ์–ด

์•ฝ์–ด ํ’€๋„ค์ž„ ์˜๋ฏธ
POR Power-On Reset ์‹œ์Šคํ…œ ์ฒซ reset
TEE Trusted Execution Environment secure ์˜์—ญ (TrustZone, SGX ๋“ฑ)
TPM Trusted Platform Module x86 ํ‘œ์ค€ ๋ณด์•ˆ chip
PCR Platform Configuration Register TPM์˜ hash accumulator
PQC Post-Quantum Cryptography ์–‘์ž ์ปดํ“จํ„ฐ ๋Œ€์‘ ์•”ํ˜ธ
TOCTOU Time-of-Check to Time-of-Use verify์™€ use ์‚ฌ์ด race ๊ณต๊ฒฉ
JTAG Joint Test Action Group debug interface (๋ณด์•ˆ ์œ„ํ˜‘ ํฌํ•จ)

์ถ”๊ฐ€ ํ•ญ๋ชฉ (Phase 2 ๊ฒ€์ˆ˜ ์™„๋ฃŒ)

BootROM

Definition. SoC ์˜ ์ฒซ ๋ถ€ํŒ… ๋‹จ๊ณ„๋กœ ๋™์ž‘ํ•˜๋Š” immutable ์ฝ”๋“œ ์˜์—ญ์œผ๋กœ, RoT ๊ฒ€์ฆ์˜ ์‹œ์ž‘์ ์ด ๋˜๋ฉฐ fuse / OTP ์— ๊ธฐ๋ก๋œ ๊ณต๊ฐœํ‚ค ํ•ด์‹œ๋กœ ๋‹ค์Œ ๋‹จ๊ณ„ ์ด๋ฏธ์ง€์˜ ์„œ๋ช…์„ ๊ฒ€์ฆํ•œ๋‹ค.

Source. ARM Trusted Firmware-A (BL1); SoC vendor BootROM specs.

Related. RoT, eFuse, OTP, BL1, secure boot.

See also. Module 01

JTAG

Definition. IEEE 1149.1 ๊ธฐ๋ฐ˜ boundary-scan ๋””๋ฒ„๊ทธ ์ธํ„ฐํŽ˜์ด์Šค๋กœ, secure boot ํ™˜๊ฒฝ์—์„œ๋Š” fuse ๋˜๋Š” ์ธ์ฆ challenge ๋กœ ๋น„ํ™œ์„ฑํ™”/์ œํ•œํ•ด์•ผ ํ•˜๋Š” ์ž ์žฌ์  ๊ณต๊ฒฉ๋ฉด์ด๋‹ค.

Source. IEEE Std 1149.1; SoC vendor security guides.

Related. Debug Authentication, JTAG locking, attack surface.

See also. Module 01, Module 05

PUF (Physically Unclonable Function)

Definition. ์นฉ ์ œ์กฐ ๋ณ€๋™์„ฑ์—์„œ ๋น„๋กฏ๋˜๋Š” ๊ณ ์œ ํ•œ ๋ฌผ๋ฆฌ ์‘๋‹ต์„ ํ‚ค ๋˜๋Š” ์‹๋ณ„์ž๋กœ ์ถ”์ถœํ•˜๋Š” ํšŒ๋กœ๋กœ, ํ‰๋ฌธ ํ‚ค๋ฅผ ๋ฉ”๋ชจ๋ฆฌ์— ์ €์žฅํ•˜์ง€ ์•Š์•„๋„ chip-unique secret ์„ ๋ณต์›ํ•  ์ˆ˜ ์žˆ๋‹ค.

Source. Suh & Devadas, "Physical Unclonable Functions for Device Authentication", DAC 2007; SoC vendor security IP.

Related. HUK, eFuse, key provisioning.

See also. Module 01

TOCTOU (Time-of-Check-to-Time-of-Use)

Definition. ๊ฒ€์ฆ(Time of Check)๊ณผ ์‚ฌ์šฉ(Time of Use) ์‚ฌ์ด์— ๊ณต๊ฒฉ์ž๊ฐ€ ๋Œ€์ƒ์„ ๋ณ€๊ฒฝํ•ด ๊ฒ€์ฆ ๊ฒฐ๊ณผ๋ฅผ ๋ฌด๋ ฅํ™”ํ•˜๋Š” ์ทจ์•ฝ์  ํด๋ž˜์Šค.

Source. McPhee, "Operating System Integrity in OS/VS2", IBM Systems Journal 1974.

Related. Race condition, double-fetch, secure copy-then-verify.

See also. Module 05

EL1 (Exception Level 1)

Definition. ARMv8 / ARMv9 ์˜ 4-level ์˜ˆ์™ธ ๋ชจ๋ธ ์ค‘ OS ์ปค๋„์ด ๋™์ž‘ํ•˜๋Š” ๋ ˆ๋ฒจ๋กœ, Normal World ์—์„  Linux/RTOS ๊ฐ€, Secure World ์—์„  Trusted OS ๊ฐ€ ์œ„์น˜ํ•œ๋‹ค.

Source. ARM ARM (Architecture Reference Manual) โ€” Exception Levels.

Related. EL0, EL2, EL3, TrustZone, S-EL1.

See also. Module 02

EL3 (Exception Level 3)

Definition. ARMv8/v9 ์ตœ์ƒ์œ„ ์˜ˆ์™ธ ๋ ˆ๋ฒจ๋กœ, Secure Monitor (TF-A ์˜ BL31) ๊ฐ€ ๋™์ž‘ํ•˜๋ฉฐ Normal World โ†” Secure World ์ „ํ™˜์„ ์ค‘์žฌํ•œ๋‹ค.

Source. ARM ARM โ€” Exception Levels; ARM Trusted Firmware-A.

Related. Secure Monitor, BL31, SMC, TrustZone.

See also. Module 02

DSA (Digital Signature Algorithm)

Definition. NIST FIPS 186 ์— ์ •์˜๋œ ์ด์‚ฐ๋Œ€์ˆ˜ ๊ธฐ๋ฐ˜ ์„œ๋ช… ์•Œ๊ณ ๋ฆฌ์ฆ˜ ๊ตฐ์˜ ์ด์นญ์œผ๋กœ, ๋ณธ ๊ฐ•์˜์—์„œ๋Š” RSA / ECDSA / ML-DSA(PQC) ์˜ ์ƒ์œ„ ์นดํ…Œ๊ณ ๋ฆฌ๋กœ ์‚ฌ์šฉํ•œ๋‹ค.

Source. NIST FIPS 186-5 โ€” Digital Signature Standard.

Related. RSA, ECDSA, ML-DSA, signing, verification.

See also. Module 03

PQC (Post-Quantum Cryptography)

Definition. ์–‘์ž ์ปดํ“จํŒ… ๊ณต๊ฒฉ์— ๊ฒฌ๋””๋„๋ก ์„ค๊ณ„๋œ ๊ณต๊ฐœํ‚ค ์•Œ๊ณ ๋ฆฌ์ฆ˜ ๊ตฐ์œผ๋กœ, NIST ํ‘œ์ค€ํ™”์—์„œ๋Š” ML-KEM(ํ‚ค ๊ตํ™˜), ML-DSA(์„œ๋ช…) ๊ฐ€ ์ฑ„ํƒ๋˜์—ˆ๋‹ค.

Source. NIST PQC Standardization; FIPS 203, 204, 205.

Related. ML-DSA, ML-KEM, SLH-DSA, lattice-based crypto.

See also. Module 03

RPMB (Replay Protected Memory Block)

Definition. eMMC / UFS ๋””๋ฐ”์ด์Šค์˜ ์ธ์ฆ ํ‚ค ๊ธฐ๋ฐ˜ ์˜์—ญ์œผ๋กœ, host ์™€ ๊ณต์œ  secret ์œผ๋กœ read/write ์ธ์ฆ์„ ์ˆ˜ํ–‰ํ•ด rollback / replay ๊ณต๊ฒฉ์„ ๋ง‰๋Š”๋‹ค.

Source. JEDEC eMMC 5.1 (JESD84-B51); UFS Spec โ€” RPMB.

Related. Secure storage, anti-rollback, monotonic counter.

See also. Module 04

FIP (Firmware Image Package)

Definition. ARM TF-A ๊ฐ€ ์‚ฌ์šฉํ•˜๋Š” ๋‹จ์ผ binary container ํฌ๋งท์œผ๋กœ, BL2 / BL31 / BL33 ๋“ฑ ๋ถ€ํŒ… ๋‹จ๊ณ„๋ณ„ ์ด๋ฏธ์ง€๋ฅผ ๋ฌถ๊ณ  ๊ฐ๊ฐ์˜ ๋ฌด๊ฒฐ์„ฑ ์ธ์ฆ์„œ๋ฅผ ํฌํ•จํ•œ๋‹ค.

Source. ARM Trusted Firmware-A documentation, Firmware Design โ€” FIP.

Related. TF-A, BL2, BL31, BL33, certificate.

See also. Module 04

PCR (Platform Configuration Register)

Definition. TPM ๋˜๋Š” ๋™๋“ฑํ•œ ์ธก์ • ์ €์žฅ์†Œ ๋‚ด์˜ ๋ˆ„์  ํ•ด์‹œ ๋ ˆ์ง€์Šคํ„ฐ๋กœ, ๋ถ€ํŒ… ๋‹จ๊ณ„๋งˆ๋‹ค ์ธก์ •๊ฐ’์„ extend ํ•˜์—ฌ Attestation / Sealed Storage ์˜ ๊ธฐ์ค€๊ฐ’์œผ๋กœ ์‚ฌ์šฉ๋œ๋‹ค.

Source. TCG TPM 2.0 Library Specification.

Related. TPM, Measured Boot, Attestation, Extend operation.

See also. Module 02

BL31 (TF-A Boot Loader stage 3-1)

Definition. ARM Trusted Firmware-A ์—์„œ EL3 ์— ์ƒ์ฃผํ•˜๋Š” Secure Monitor ๋‹จ๊ณ„๋กœ, BL2 ๊ฐ€ ๋กœ๋“œํ•œ ํ›„ ๋ถ€ํŒ… ์ข…๋ฃŒ ์‹œ์ ๊นŒ์ง€ SMC ํ•ธ๋“ค๋ง๊ณผ Power State Coordination(PSCI) ์„ ๋‹ด๋‹นํ•œ๋‹ค.

Source. ARM Trusted Firmware-A documentation.

Related. Secure Monitor, BL2, BL33, PSCI, SMC.

See also. Module 02

BL33 (TF-A Boot Loader stage 3-3)

Definition. TF-A ์—์„œ BL31 ๋‹ค์Œ์œผ๋กœ ์‹คํ–‰๋˜๋Š” Non-secure bootloader ๋‹จ๊ณ„๋กœ, ์ผ๋ฐ˜์ ์œผ๋กœ U-Boot / EDK2 ๊ฐ€ ์œ„์น˜ํ•˜์—ฌ OS loader ๊นŒ์ง€ ์ธ๊ณ„ํ•œ๋‹ค.

Source. ARM Trusted Firmware-A documentation.

Related. U-Boot, EDK2, BL31, BL32, OS loader.

See also. Module 02

TPM (Trusted Platform Module)

Definition. TCG ํ‘œ์ค€์ด ์ •์˜ํ•œ ๋ณด์•ˆ ์ฝ”ํ”„๋กœ์„ธ์„œ / ํŽŒ์›จ์–ด๋กœ, ํ‚ค ๋ณด๊ด€ยท์„œ๋ช…ยทattestationยทPCR-based measured boot ๋ฅผ ์ œ๊ณตํ•œ๋‹ค.

Source. TCG TPM 2.0 Library Specification.

Related. PCR, Attestation, Sealed Storage.

See also. Module 02

NIST FIPS ์‹œ๋ฆฌ์ฆˆ (203 / 204 / 205)

Definition. NIST ๊ฐ€ ์ œ์ •ํ•œ PQC ํ‘œ์ค€ โ€” FIPS 203 ML-KEM (key encapsulation), FIPS 204 ML-DSA (signature, lattice), FIPS 205 SLH-DSA (signature, hash-based).

Source. NIST FIPS 203, 204, 205 (2024).

Related. ML-KEM, ML-DSA, SLH-DSA, PQC.

See also. Module 03

BL32 (Trusted OS, e.g. OP-TEE)

Definition. TF-A ์˜ Secure World OS ๋‹จ๊ณ„๋กœ, BL31 ์ด ์ง„์ž…์ ์„ ํ˜ธ์ถœํ•˜๋ฉด EL1S ์—์„œ Trusted Application ์„ ํ˜ธ์ŠคํŒ…ํ•œ๋‹ค (๋Œ€ํ‘œ ๊ตฌํ˜„: OP-TEE).

Source. ARM Trusted Firmware-A documentation; OP-TEE documentation.

Related. OP-TEE, S-EL1, BL31, TEE.

See also. Module 02

NS bit (Non-Secure Bit, TrustZone)

Definition. ARM TrustZone ์˜ ํ•ต์‹ฌ ๋น„ํŠธ๋กœ, AXI / AHB transaction ์˜ ๋ณด์•ˆ ๋„๋ฉ”์ธ (Secure / Non-Secure) ์„ ํ‘œํ˜„ํ•˜๋ฉฐ TZ aware peripheral ์˜ ์ ‘๊ทผ ๊ถŒํ•œ ๊ฒฐ์ •์— ์‚ฌ์šฉ๋œ๋‹ค.

Source. ARM TrustZone Architecture; AMBA NSAID extension.

Related. TrustZone, S/NS, NSAID.

See also. Module 02